FPGA发端设计

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接收机与FPGA

目录

作业要求

具体实现

发送的10101数据从txt文件中读取

  • MATLAB仿真
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    data_len = 1024;        %数据长度
    data = randi([0 1],1,data_len); 
    fid = fopen('send_data.txt', 'w'); %创建txt文件
    for i = 1:length(data)
        if(i < length(data))
            fprintf(fid,'%d\n',data(i));
        else
            fprintf(fid,'%d',data(i));
        end
    end  
    % fprintf(fid,'%d\n',sin_14bit);
    fclose(fid);

    生成1024个0，1随机数，生成txt文件；
    生成之后需要对发送序列进行映射，然后上采样，此处设计为4倍上采样

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    data = importdata('send_data.txt');
    data_1 = (data'-1/2)*2;
    data_up = upsample(data_1,4);
  • Verilog实现

    读取txt文件在仿真文件中实现，映射及上采样代码在设计文件中实现

    • Design文件

      核心代码

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      //映射0变-1 + 4倍上采样
      reg [1:0] data_map = 2'b00;  //映射加插值后的信号
      reg [1:0] cnt = 2'b00;   //计数，4为一个周期
      always @(posedge clk) begin
          if (rst == 1'b1) begin
              data_map <= 2'b00;
              cnt <= 2'b00;       
          end
          else begin
              case(cnt)
              2'b01:begin
                  if(data == 1'b1&&data_nd == 1'b1)begin
                      data_map <=2'b01;
                      cnt <= cnt + 2'b01;
                  end                            //data为1时不变
                  else if(data_nd == 1'b1) begin
                      data_map <= 2'b11;
                      cnt <= cnt +2'b01;
                  end                            //data为0时变为-1
              end    
              default:begin
                  cnt <= cnt +2'b01;
                  data_map <= 2'b00;
                  end    
              endcase       
          end
      end

    • Testbench文件

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      module tb_bpsk_send(
          );
      reg clk;
      reg rst;
      reg data = 1'b0;    
      initial begin
          clk = 1'b0;
        end
      always #10 clk = ~clk;    //50MHz clock
        initial begin
          rst = 1'b1;
          #200
          rst = 1'b0;
        end 
      reg  [1-1:0] data_mem [0:1023] ;//定义一个位宽为2bit，深度为1024的mem
      initial begin
           $readmemh("G:/vivado_project/bpsk/bpsk.srcs/sources_1/send_data.txt",data_mem);
      end
      integer i;
      reg [1:0] counter = 2'd0;
      reg data_nd = 1'b0;
      always @(posedge clk) begin
         if (rst|i==1023) begin
            data <= 1'b0;
            i <= 0; 
            counter <= 2'd0; 
            data_nd <= 1'b0;   
         end
         else begin
            case(counter)
               2'd1:begin
                  data <= data_mem[i];
                  i <= i + 1;
                  counter <= counter + 2'd1;
                  data_nd <= 1'b1; //数据有效使能
               end
               default:begin
                  counter <= counter + 2'd1;
               end
            endcase
         end
      end

      wire [23:0] s_up;

      bpsk_send bpsk_send_m(
          .clk(clk),
          .rst(rst),
          .data(data),
          .data_nd(data_nd),

          .s_up(s_up)
      ); 

      endmodule

    • 仿真波形

使用FIR核进行根升余弦

  • Matlab
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    alfs = 0.35;            % 滚降系数
    osr = 4;             
    fir_rcos = rcosdesign(alfs,6,osr,"sqrt");
    max_fir_rcos = max(abs(fir_rcos));
    fir_rcos_bit = round((2^7-1)*fir_rcos/max_fir_rcos); %8bit量化
    fid = fopen('fir_data.coe', 'w'); %创建COE文件
    fprintf(fid, 'Radix=10;\n');
    fprintf(fid, 'CoefData=\n');
    for i = 1:length(fir_rcos_bit)
        if(i < length(fir_rcos_bit))
            fprintf(fid,'%d\n',fir_rcos_bit(i));
        else
            fprintf(fid,'%d',fir_rcos_bit(i));
        end
    end  
    % fprintf(fid,'%d\n',sin_14bit);
    fclose(fid);

    data_bx = conv(fir_rcos_bit,data_up);                 %通过滤波器

  • verilog实现

    • Design

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      //根升余弦滤波FIR
      wire s_axis_data_tready;
      wire m_axis_data_tvalid;
      wire [15:0] fir_out;
      shape_fir shape_fir_m (
        .aclk(clk),                              // input wire aclk
        .s_axis_data_tvalid(1'b1),  // input wire s_axis_data_tvalid
        .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
        .s_axis_data_tdata({6'b0,data_map}),    // input wire [7 : 0] s_axis_data_tdata
        .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
        .m_axis_data_tdata(fir_out)    // output wire [15 : 0] m_axis_data_tdata
      );

    • IP核设置

      仿真通道文件和之前一样，为了检查错误，加了一个计数器用于检测

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      //用于观察的计数器
      reg [32:0] cnt_1 = 33'd0;
      always @(posedge clk) begin
         if(rst)begin
            cnt_1 <= 33'd0;
         end
         else begin
            cnt_1 <= cnt_1 + 33'd1;
         end
      end

    • 仿真输出

采用DDS生成中频载波

  • MATLAB

    生成载波序列，并对其量化，产生coe文件

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    fs = 16000;            % 采样率
    fc = 2000;             % 载波频率
    t = 0:length(data_bx)-1;
    carrier = cos(2*pi*fc/fs*t);                      %载波
    cos_bit = round((2^7-1)*carrier/max(abs(carrier)));%8bit量化

    fid = fopen('cos_bit.coe', 'w'); %创建COE文件
    fprintf(fid, 'memory_initialization_radix=10;\n');
    fprintf(fid, 'memory_initialization_vector=\n');
    for i = 1:length(cos_bit)
        if(i < length(cos_bit))
            fprintf(fid,'%d\n',cos_bit(i));
        else
            fprintf(fid,'%d',cos_bit(i));
        end
    end  
    % fprintf(fid,'%d\n',cos_bit);
    fclose(fid);
    plot(cos_bit);

  • verilog

    • design

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      //DDS生成中频载波
      reg [12:0] addra;
      wire [7:0] cos_out;
      reg [7:0] cook;
      parameter add_M = 1;
      always @(posedge clk) begin
         if (rst|addra==13'd4119) begin
            addra <= 13'd0; 
            cook <= 8'd0;   
         end
         else if(cook==8'd22) begin
            addra <= addra + add_M;
         end
         else begin
            addra <= addra;
            cook <= cook + 8'd1;
         end
      end
      cos_local cos_local_m (
        .clka(clk),    // input wire clka
        .ena(1'b1),      // input wire ena
        .addra(addra),  // input wire [12 : 0] addra
        .douta(cos_out)  // output wire [7 : 0] douta
      );

    • 仿真输出

乘法器实现上变频

  • MATLAB

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    s_up = data_bx .* cos_bit;

  • Verilog

    Design

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    //乘法器
    //wire [23:0] s_up;
    mult_s mult_s_m (
      .CLK(clk),  // input wire CLK
      .A(fir_out),      // input wire [15 : 0] A
      .B(cos_out),      // input wire [7 : 0] B
      .P(s_up)      // output wire [23 : 0] P
    );

    IP核设置

  • 仿真输出

结果验证

首先需要在vivado中输出txt文件

  • MATLAB
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    data_out = importdata("test.txt");
    y = s_up - data_out';
    plot(y);

    这张图出现的原因是输入数据为1024，4倍上采样之后为4096个点，理论上通过滤波器之后应该是4096个点，但MATLAB中卷积之后为4120个点，滤波器两边的拖尾造成

  • Verilog
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    reg [14:0] counter_1;
    reg [32:0] cnt_1 = 33'd0;
    always @(posedge clk) begin
        if (rst) begin
           counter_1 <= 15'd0;
        end
        else if (cnt_1 == 33'd4160) begin
          $fclose(save_file);
        end
        else begin
    //       $fdisplay(save_file,"%d",$signed(s_up));
            $fwrite(save_file,"%d\n",$signed(s_up)); 
        end
    end   
    //用于观察的计数器

    always @(posedge clk) begin
       if(rst)begin
          cnt_1 <= 33'd0;
       end
       else begin
          cnt_1 <= cnt_1 + 33'd1;
       end
    end

附录

MATLAB

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clc;clear;close all;
% data_len = 1024;        %数据长度
% data = randi([0 1],1,data_len); 
% fid = fopen('send_data.txt', 'w'); %创建COE文件
% for i = 1:length(data)
%     if(i < length(data))
%         fprintf(fid,'%d\n',data(i));
%     else
%         fprintf(fid,'%d',data(i));
%     end
% end  
% % fprintf(fid,'%d\n',sin_14bit);
% fclose(fid);
% CreatCodeFile(data,'data.coe',10);
data = importdata('send_data.txt');
%% 根升余弦滤波器
alfs = 0.35;            % 滚降系数
osr = 4;             
fir_rcos = rcosdesign(alfs,6,osr,"sqrt");
max_fir_rcos = max(abs(fir_rcos));
fir_rcos_bit = round((2^7-1)*fir_rcos/max_fir_rcos); %8bit量化
% fid = fopen('fir_data.coe', 'w'); %创建COE文件
% fprintf(fid, 'Radix=10;\n');
% fprintf(fid, 'CoefData=\n');
% for i = 1:length(fir_rcos_bit)
%     if(i < length(fir_rcos_bit))
%         fprintf(fid,'%d\n',fir_rcos_bit(i));
%     else
%         fprintf(fid,'%d',fir_rcos_bit(i));
%     end
% end  
% % fprintf(fid,'%d\n',sin_14bit);
% fclose(fid);
data_1 = (data'-1/2)*2;
data_up = upsample(data_1,4);
data_bx = conv(fir_rcos_bit,data_up);                 %通过滤波器
fs = 16000;            % 采样率
fc = 2000;             % 载波频率
t = 0:length(data_bx)-1;
carrier = cos(2*pi*fc/fs*t);                      %载波
cos_bit = round((2^7-1)*carrier/max(abs(carrier)));%8bit量化
% fid = fopen('cos_bit.coe', 'w'); %创建COE文件
% fprintf(fid, 'memory_initialization_radix=10;\n');
% fprintf(fid, 'memory_initialization_vector=\n');
% for i = 1:length(cos_bit)
%     if(i < length(cos_bit))
%         fprintf(fid,'%d\n',cos_bit(i));
%     else
%         fprintf(fid,'%d',cos_bit(i));
%     end
% end  
% % fprintf(fid,'%d\n',cos_bit);
% fclose(fid);
% plot(cos_bit);
s_up = data_bx .* cos_bit;
data_out = importdata("test.txt");
y = s_up - data_out';
plot(y);

Verilog

Design

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module bpsk_send(
    input clk,
    input rst,            //低有效
    input data,
    input data_nd,
    output [23:0] s_up
    );   
//映射0变-1 + 4倍上采样
reg [1:0] data_map = 2'b00;  //映射加插值后的信号
reg [1:0] cnt = 2'b00;   //计数，4为一个周期
always @(posedge clk) begin
    if (rst == 1'b1) begin
        data_map <= 2'b00;
        cnt <= 2'b00;       
    end
    else begin
        case(cnt)
        2'b01:begin
            if(data == 1'b1&&data_nd == 1'b1)begin
                data_map <=2'b01;
                cnt <= cnt + 2'b01;
            end                            //data为1时不变
            else if(data_nd == 1'b1) begin
                data_map <= 2'b11;
                cnt <= cnt +2'b01;
            end                            //data为0时变为-1
        end    
        default:begin
            cnt <= cnt +2'b01;
            data_map <= 2'b00;
            end    
        endcase       
    end
end   
//根升余弦滤波FIR
wire s_axis_data_tready;
wire m_axis_data_tvalid;
wire [15:0] fir_out;
shape_fir shape_fir_m (
  .aclk(clk),                              // input wire aclk
  .s_axis_data_tvalid(1'b1),  // input wire s_axis_data_tvalid
  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
  .s_axis_data_tdata({6'b0,data_map}),    // input wire [7 : 0] s_axis_data_tdata
  .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
  .m_axis_data_tdata(fir_out)    // output wire [15 : 0] m_axis_data_tdata
);
//DDS生成中频载波
reg [12:0] addra;
wire [7:0] cos_out;
reg [7:0] cook;          //用于截断有效数据的计数标志
parameter add_M = 1;
    always @(posedge clk) begin
        if (rst||addra==13'd4119) begin
           addra <= 13'd0; 
           cook <= 8'd0;   
        end
        else if(cook==8'd22) begin
           addra <= addra + add_M;
        end
        else begin
           addra <= addra;
           cook <= cook + 8'd1;
        end
    end
cos_local cos_local_m (
  .clka(clk),    // input wire clka
  .ena(1'b1),      // input wire ena
  .addra(addra),  // input wire [12 : 0] addra
  .douta(cos_out)  // output wire [7 : 0] douta
);

//乘法器
//wire [23:0] s_up;
mult_s mult_s_m (
  .CLK(clk),  // input wire CLK
  .A(fir_out),      // input wire [15 : 0] A
  .B(cos_out),      // input wire [7 : 0] B
  .P(s_up)      // output wire [23 : 0] P
);  
    
endmodule

Testbench

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`timescale 1ns / 1ps
module tb_bpsk_send(
    );
reg clk;
reg rst;
reg data = 1'b0;    
initial begin
    clk = 1'b0;
  end
always #10 clk = ~clk;    //50MHz clock
  initial begin
    rst = 1'b1;
    #200
    rst = 1'b0;
  end 
reg  [1-1:0] data_mem [0:1023] ;//定义一个位宽为2bit，深度为1024的mem
initial begin
     $readmemh("G:/vivado_project/bpsk/bpsk.srcs/sources_1/send_data.txt",data_mem);
end
integer i;
//reg [1:0] counter = 2'd0;
//always @(posedge clk) begin
//   if (rst|i==1023) begin
//      data <= 1'b0;
//      i <= 0; 
//      counter <= 2'd0;    
//   end
//   else begin
//      i <= i + 1;
//      data <= data_mem[i];    
//   end
//end
reg [1:0] counter = 2'd0;
reg data_nd = 1'b0;
always @(posedge clk) begin
   if (rst|i==1023) begin
      data <= 1'b0;
      i <= 0; 
      counter <= 2'd0; 
      data_nd <= 1'b0;   
   end
   else begin
      case(counter)
         2'd1:begin
            data <= data_mem[i];
            i <= i + 1;
            counter <= counter + 2'd1;
            data_nd <= 1'b1; 
         end
         default:begin
            counter <= counter + 2'd1;
         end
      endcase
   end
end

wire [23:0] s_up;

bpsk_send bpsk_send_m(
    .clk(clk),
    .rst(rst),
    .data(data),
    .data_nd(data_nd),

    .s_up(s_up)
);    
integer save_file;
initial begin
    save_file = $fopen("G:/vivado_project/bpsk/bpsk.srcs/sources_1/test.txt");    //打开所创建的文件；若找不到该文件，则会自动创建该文件。
    if(save_file == 0)begin 
        $display ("can not open the file!");    //如果创建文件失败，则会显示"can not open the file!"信息。
        $stop;
    end
end
reg [14:0] counter_1;
reg [32:0] cnt_1 = 33'd0;
always @(posedge clk) begin
    if (rst) begin
       counter_1 <= 15'd0;
    end
    else if (cnt_1 == 33'd4160) begin
      $fclose(save_file);
    end
    else begin
//       $fdisplay(save_file,"%d",$signed(s_up));
        $fwrite(save_file,"%d\n",$signed(s_up)); 
    end
end   
//用于观察的计数器

always @(posedge clk) begin
   if(rst)begin
      cnt_1 <= 33'd0;
   end
   else begin
      cnt_1 <= cnt_1 + 33'd1;
   end
end

endmodule

代码优化及思考

目录

MATLAB代码基本不变，主要是verilog代码
（直接数据输入，上采样环节在IP核中设置）

HDL

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reg [1:0] data_map = 2'b00;   //映射之后的序列
always @(posedge clk) begin
    if (rst == 1'b1) begin
        data_map <= 2'b00;     
    end
    else begin
        case(data_nd)
        1'b1:begin
            if(data == 1'b1)begin
                data_map <=2'b01;
            end                            //data为1时变 1
            else begin
                data_map <= 2'b11;
            end                            //data为0时变-1
        end    
        default:begin
            data_map <= 2'b00;
            end    
        endcase       
    end
end

映射序列的写法

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wire [1:0] data_map ;
assign data_map = data ? 2'b01 : 2'b11 ;
//映射0变-1；

  • 结果输出

IP核设置（FIR）

  • 内插倍数设置为4

  • 输出结果 （错误→正确）

    ⁉️输出序列是错的
    🚗找了好久，序列的前三个数与MATLAB数据就差个负号，以为是映射方式错了，改了半天，原来是使能信号，修改如下；

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    fir_compiler_0 fir_compiler (
      .aclk(clk),                              // input wire aclk
      .s_axis_data_tvalid(data_nd),  // input wire s_axis_data_tvalid
      .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
      .s_axis_data_tdata({6'd0,data_map}),    // input wire [7 : 0] s_axis_data_tdata
      .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
      .m_axis_data_tdata(fir_out)    // output wire [15 : 0] m_axis_data_tdata
    );

代码附录

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module bpsk_send(
    input clk,
    input rst,
    input data,
    input data_nd   
    );
// reg [1:0] data_map = 2'b00;   //映射之后的序列
// always @(posedge clk) begin
//     if (rst == 1'b1) begin
//         data_map <= 2'b00;     
//     end
//     else begin
//         case(data_nd)
//         1'b1:begin
//             if(data == 1'b1)begin
//                 data_map <=2'b01;
//             end                            //data为1时变 1
//             else begin
//                 data_map <= 2'b11;
//             end                            //data为0时变-1
//         end    
//         default:begin
//             data_map <= 2'b00;
//             end    
//         endcase       
//     end
// end
wire [1:0] data_map ;
assign data_map = data ? 2'b01 : 2'b11 ;
//FIR根生余弦成形
wire    s_axis_data_tready;
wire    m_axis_data_tvalid;  
wire [15:0]    fir_out;
fir_compiler_0 fir_compiler (
  .aclk(clk),                              // input wire aclk
  .s_axis_data_tvalid(data_nd),  // input wire s_axis_data_tvalid
  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
  .s_axis_data_tdata({6'd0,data_map}),    // input wire [7 : 0] s_axis_data_tdata
  .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
  .m_axis_data_tdata(fir_out)    // output wire [15 : 0] m_axis_data_tdata
);

//DDS生成中频载波
    reg [12:0] addra = 13'd0;
    wire [7:0] cos_out;
    parameter add_M = 1;
    always @(posedge clk) begin
        if (rst||addra==13'd4119) begin
           addra <= 13'd0;    
        end
        else if(m_axis_data_tvalid) begin
           addra <= addra + add_M;
        end
        else begin
           addra <= addra;
        end
    end
gen_cos gen_cos_m (
  .clka(clk),    // input wire clka
  .ena(m_axis_data_tvalid),      // input wire ena
  .addra(addra),  // input wire [12 : 0] addra
  .douta(cos_out)  // output wire [7 : 0] douta
);

//延时一个周期
reg [7:0] cos_delay = 8'd0;
always @(posedge clk) begin
    if(rst) begin
        cos_delay <= 8'd0;
    end
    else begin
        cos_delay <= cos_out;
    end
end

testbench

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module tb_bpsk_send(
 );
   reg clk;
   reg rst;
   reg  data = 1'b0;
   reg  data_mem [1023:0];
   initial begin
      clk = 0;
      rst = 1;
      $readmemb("G:/vivado_project/bpsk_send/bpsk_send.srcs/sim_1/new/send_data.txt",data_mem);
      #200
      rst = 0;
   end 
   always #10 clk = ~ clk;

   reg [9:0] index = 10'd0;
   reg data_nd = 1'b0;
   always @(posedge clk) begin
      if (rst) begin
         data <= 1'b0;
         index <= 10'd0; 
         data_nd <= 1'b0;   
      end
      else begin
               index <= index + 1;
               data <= data_mem[index];
               data_nd <= 1'b1; 
      end
   end

    bpsk_send bpsk_send_m(
       .clk(clk),
       .rst(rst),
       .data(data),
       .data_nd(data_nd)
       );

   reg [30:0] cnt ;
   always @(posedge clk) begin
      if(rst)begin
         cnt <= 31'd0;
      end
      else begin
         cnt <= cnt + 31'd1;
      end
   end

endmodule

代码学习

读写txt文件

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//testbench
`timescale 1ns/1ps
module Recv_tb ();
    reg clk;
    reg rst;
    reg [319:0] din_da;
    reg [319:0] din_da_memory [1023:0];

    parameter START_TIME = 40;
    parameter INTERVAL = 1000;
    parameter IS_POINT = 1;

    integer handle01;

    Recv Recv_m(
        .clk(clk),
        .rst(rst),

        .din_da(din_da)
    );

    initial begin
        clk = 0;
        rst = 0;
        din_da = 0;
        $readmemb("G:/Match_Filter/Matlab/Testbench/din_da.txt",din_da_memory);
        handle01 = $fopen("G:/Match_Filter/Output_data/dout_I.txt","w");$fclose(handle01);       

        #20;
        rst = 1;
        #50;
        rst = 0;
    end

    always #1 clk = ~clk;

    reg [9:0] index = 0;
    always @(posedge clk) begin
        if(rst)begin
            din_da <= 320'd0;
            index <= 10'd0;
        end
        else begin
            index <= index + 1'b1;
            din_da <= din_da_memory[index];
        end
    end

    reg [30:0] cnt_global = 31'd0;
    always @(posedge clk) begin
        cnt_global <= cnt_global + 31'd1;                         
    end

    always @(posedge clk) begin
        if(IS_POINT)begin
            if(cnt_global == 31'd40)begin
                $fopen("G:/Match_Filter/Output_data/dout_I.txt","a+");
            end
            else if(cnt_global >= 31'd40 && cnt_global <= 31'd1040)begin
                $fwrite(handle01,"%d\n",$signed(Recv_tb.Recv_m.Match_filter_top_m.dout_I_01));
            end
            else begin
                $fclose(handle01);
            end
        end
    end
endmodule

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