滤波器设计实例

FIR滤波器设计

本文主要实现一个 8阶对称系数的并行 FIR 滤波器设计，具体实现代码如下：

module fir_parallel #(
    parameter IDATA_WIDTH = 12,  //输入数据带宽
    parameter OUT_WIDTH   = 27   //输出数据带宽
) (
    input                        clk,
    input                        rst,
    input      [IDATA_WIDTH-1:0] fir_in,
    output reg [  OUT_WIDTH-1:0] fir_out
);
    parameter PDATA_WIDTH = 13;  //处理系数位宽
    parameter FIR_TAP = 8;  //FIR抽头
    parameter FIR_TAPHALF = FIR_TAP / 2;  //FIR抽头的一半
    parameter COEFF_WIDTH = 12;  //FIR系数位宽

    //-------------滤波器系数
    parameter cof1 = 12'd41;
    parameter cof2 = 12'd132;
    parameter cof3 = 12'd341;
    parameter cof4 = 12'd510;

    reg  [              IDATA_WIDTH-1:0] fir_in_reg;
    reg  [              PDATA_WIDTH-1:0] shift_buf  [FIR_TAP-1:0];  //定义一个8位的移位寄存器
    wire [              PDATA_WIDTH-1:0] add07;
    wire [              PDATA_WIDTH-1:0] add16;
    wire [              PDATA_WIDTH-1:0] add25;
    wire [              PDATA_WIDTH-1:0] add34;

    wire [PDATA_WIDTH + COEFF_WIDTH-1:0] mul1;
    wire [PDATA_WIDTH + COEFF_WIDTH-1:0] mul2;
    wire [PDATA_WIDTH + COEFF_WIDTH-1:0] mul3;
    wire [PDATA_WIDTH + COEFF_WIDTH-1:0] mul4;

    integer i, j;

    always @(posedge clk or negedge rst) begin
        if (rst) begin
            fir_in_reg <= 12'd0;
        end else begin
            fir_in_reg <= fir_in;
        end
    end

    always @(posedge clk or negedge rst) begin
        if (rst) begin
            for (i = 0; i <= FIR_TAP - 1; i = i + 1) begin
                shift_buf[i] <= 13'd0;
            end
        end else begin
            for (j = 0; j <= FIR_TAP - 1; j = j + 1) begin
                shift_buf[j+1] <= shift_buf[j];
            end
            shift_buf[0] <= {fir_in_reg[IDATA_WIDTH-1], fir_in_reg};//扩展到13bit
        end
    end

    assign add07 = shift_buf[0] + shift_buf[7];
    assign add16 = shift_buf[1] + shift_buf[6];
    assign add25 = shift_buf[2] + shift_buf[5];
    assign add34 = shift_buf[3] + shift_buf[4];

    //25bit
    mult_gen u_mult_gen_1 (.CLK(clk),   .A(cof1),   .B(add07),  .P(mul1));
    mult_gen u_mult_gen_2 (.CLK(clk),   .A(cof2),   .B(add16),  .P(mul2));
    mult_gen u_mult_gen_3 (.CLK(clk),   .A(cof3),   .B(add25),  .P(mul3));
    mult_gen u_mult_gen_4 (.CLK(clk),   .A(cof4),   .B(add34),  .P(mul4));

    //相加多一位,变成26bit
    wire [25:0] add_mul12 = {mul1[24], mul1} + {mul2[24], mul2};
    wire [25:0] add_mul34 = {mul3[24], mul3} + {mul4[24], mul4};

    always @(posedge clk or negedge rst) begin
        if (rst) begin
            fir_out <= 27'd0;
        end else begin
            fir_out <= {add_mul12[25], add_mul12} + {add_mul34[25], add_mul34};//加法,bit增一位,变成27bit
        end
    end
   
endmodule